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| author | Dinh Nguyen <dinguyen@kernel.org> | 2020-07-31 18:26:40 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-09-17 14:55:25 +0300 |
| commit | 91dff93e5584278c23b1e787435210e94369de75 (patch) | |
| tree | f665fb01c2d418a73646e4cabab9aa248b246ac6 /arch | |
| parent | 1dc746dfc129ac62df219ca95ebc5b0296d68da4 (diff) | |
| download | linux-91dff93e5584278c23b1e787435210e94369de75.tar.xz | |
ARM: dts: socfpga: fix register entry for timer3 on Arria10
[ Upstream commit 0ff5a4812be4ebd4782bbb555d369636eea164f7 ]
Fixes the register address for the timer3 entry on Arria10.
Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 8f614c4b0e3e..9c71472c237b 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -819,7 +819,7 @@ timer3: timer3@ffd00100 { compatible = "snps,dw-apb-timer"; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd01000 0x100>; + reg = <0xffd00100 0x100>; clocks = <&l4_sys_free_clk>; clock-names = "timer"; resets = <&rst L4SYSTIMER1_RESET>; |