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| author | Lucas Stach <l.stach@pengutronix.de> | 2022-12-31 08:40:25 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-02-01 10:34:03 +0300 |
| commit | 02ef93c4dfb462cfe7821aa06b112c38fc44fcf2 (patch) | |
| tree | 72af1fcb3449d20bc56b71c2d04cc23adadd3f75 /arch | |
| parent | 8aa234b1a492382874545f3b1be81147e88f0db5 (diff) | |
| download | linux-02ef93c4dfb462cfe7821aa06b112c38fc44fcf2.tar.xz | |
soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD
[ Upstream commit b814eda949c324791580003303aa608761cfde3f ]
NXP internal information shows that the PHY refclk is gated by the
GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
LCDIF being already active, tie this bit to the HDMI_TX_PHY power
domain.
Fixes: e3442022f543 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions