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authorClaudiu Beznea <claudiu.beznea@microchip.com>2022-12-08 14:52:41 +0300
committerClaudiu Beznea <claudiu.beznea@microchip.com>2023-01-12 14:45:49 +0300
commit9bfa2544dbd1133f0b0af4e967de3bb9c1e3a497 (patch)
tree58d3042ad85c16bf13e5f06b80bd80512eb8c962 /arch
parent1b929c02afd37871d5afb9d498426f83432e71c2 (diff)
downloadlinux-9bfa2544dbd1133f0b0af4e967de3bb9c1e3a497.tar.xz
ARM: dts: at91: sam9x60: fix the ddr clock for sam9x60
The 2nd DDR clock for sam9x60 DDR controller is peripheral clock with id 49. Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221208115241.36312-1-claudiu.beznea@microchip.com
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/sam9x60.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
index 8f5477e307dd..37a5d96aaf64 100644
--- a/arch/arm/boot/dts/sam9x60.dtsi
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -564,7 +564,7 @@
mpddrc: mpddrc@ffffe800 {
compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
reg = <0xffffe800 0x200>;
- clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
clock-names = "ddrck", "mpddr";
};