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author | Stephen Boyd <sboyd@kernel.org> | 2021-04-28 02:34:56 +0300 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2021-04-28 02:34:56 +0300 |
commit | 3ba2d41dca14e1afbea0c41ba8164064df407c8b (patch) | |
tree | 9952ff280826db3fcaf657b19579232d72021039 /arch | |
parent | bbc3b403b096220850b82e245a1e5f09b8b216a2 (diff) | |
parent | 0ec3815a8c1d8fe7215b1748117ac14cbeeda453 (diff) | |
download | linux-3ba2d41dca14e1afbea0c41ba8164064df407c8b.tar.xz |
Merge branch 'clk-ralink' into clk-next
- Proper clk driver for Mediatek MT7621 SoCs
* clk-ralink:
MAINTAINERS: add MT7621 CLOCK maintainer
staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'
staging: mt7621-dts: make use of new 'mt7621-clk'
clk: ralink: add clock driver for mt7621 SoC
dt: bindings: add mt7621-sysc device tree binding documentation
dt-bindings: clock: add dt binding header for mt7621 clocks
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/ralink/mt7621.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index ca0ac607b0f3..5d74fc1c96ac 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void) void __init ralink_of_remap(void) { - rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); - rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc"); + rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc"); + rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc"); if (!rt_sysc_membase || !rt_memc_membase) panic("Failed to remap core resources"); @@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) { name = "MT7621"; - soc_info->compatible = "mtk,mt7621-soc"; + soc_info->compatible = "mediatek,mt7621-soc"; } else { panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1); } |