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authorMarkos Chandras <markos.chandras@imgtec.com>2014-11-05 11:25:37 +0300
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 09:44:04 +0300
commit83fd43449baaf88fe5c03dd0081a062041837c51 (patch)
treec7b79fe22f2b864d082ad7c685b3dfc66d93af5e /arch
parent7f0dd7683c4d7e01dc99d8922190af6bcc9a0860 (diff)
downloadlinux-83fd43449baaf88fe5c03dd0081a062041837c51.tar.xz
MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line
Commit de8974e3f76c0 ("MIPS: asm: r4kcache: Add EVA cache flushing functions") added cache function for EVA using the cachee instruction. However, it didn't add a case for the protected_writeback_dcache_line. mips_dsemul() calls r4k_flush_cache_sigtramp() which in turn uses the protected_writeback_dcache_line() to flush the trampoline code back to memory. This used the wrong "cache" instruction leading to random userland crashes on non-FPU cores. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8331/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/r4kcache.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 4520adc8699b..cd6e0afc6833 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -257,7 +257,11 @@ static inline void protected_flush_icache_line(unsigned long addr)
*/
static inline void protected_writeback_dcache_line(unsigned long addr)
{
+#ifdef CONFIG_EVA
+ protected_cachee_op(Hit_Writeback_Inv_D, addr);
+#else
protected_cache_op(Hit_Writeback_Inv_D, addr);
+#endif
}
static inline void protected_writeback_scache_line(unsigned long addr)