diff options
| author | Clément Léger <clement.leger@bootlin.com> | 2022-06-24 17:40:00 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-06-27 13:37:56 +0300 |
| commit | 9aab31d66ec97d7047e42feacc356bc9c21a5bf5 (patch) | |
| tree | 5d2a8314d2ad2b3d7246a4a71232716720923510 /arch | |
| parent | cf9695d8a7e927f7563ce6ea0a4e54b8214a12f1 (diff) | |
| download | linux-9aab31d66ec97d7047e42feacc356bc9c21a5bf5.tar.xz | |
ARM: dts: r9a06g032-rzn1d400-db: add switch description
Add description for the switch, GMAC2 and MII converter. With these
definitions, the switch port 0 and 1 (MII port 5 and 4) are working on
RZ/N1D-DB board.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts index 3f8f3ce87e12..4227aba70c30 100644 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -8,6 +8,8 @@ /dts-v1/; +#include <dt-bindings/pinctrl/rzn1-pinctrl.h> +#include <dt-bindings/net/pcs-rzn1-miic.h> #include "r9a06g032.dtsi" / { @@ -31,3 +33,118 @@ timeout-sec = <60>; status = "okay"; }; + +&gmac2 { + status = "okay"; + phy-mode = "gmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&switch { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_mdio1>, <&pins_eth3>, <&pins_eth4>; + + dsa,member = <0 0>; + + mdio { + clock-frequency = <2500000>; + + #address-cells = <1>; + #size-cells = <0>; + + switch0phy4: ethernet-phy@4 { + reg = <4>; + micrel,led-mode = <1>; + }; + + switch0phy5: ethernet-phy@5 { + reg = <5>; + micrel,led-mode = <1>; + }; + }; +}; + +&switch_port0 { + label = "lan0"; + phy-mode = "mii"; + phy-handle = <&switch0phy5>; + status = "okay"; +}; + +&switch_port1 { + label = "lan1"; + phy-mode = "mii"; + phy-handle = <&switch0phy4>; + status = "okay"; +}; + +&switch_port4 { + status = "okay"; +}; + +ð_miic { + status = "okay"; + renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; +}; + +&mii_conv4 { + renesas,miic-input = <MIIC_SWITCH_PORTB>; + status = "okay"; +}; + +&mii_conv5 { + renesas,miic-input = <MIIC_SWITCH_PORTA>; + status = "okay"; +}; + +&pinctrl{ + pins_mdio1: pins_mdio1 { + pinmux = < + RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH) + RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH) + >; + }; + pins_eth3: pins_eth3 { + pinmux = < + RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + >; + drive-strength = <6>; + bias-disable; + }; + pins_eth4: pins_eth4 { + pinmux = < + RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) + >; + drive-strength = <6>; + bias-disable; + }; +}; |