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| author | Sven Auhagen <Sven.Auhagen@voleatech.de> | 2020-07-21 07:40:27 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2020-07-31 11:09:00 +0300 |
| commit | 28ee8b0912ca2ff68c2c03ff97bf1c22634c7942 (patch) | |
| tree | f5d20e35e0dbc007af249cb1fc7e6af97fa36d08 /crypto/xts.c | |
| parent | c6720415907f21b9c53efbe679b96c3cc9d06404 (diff) | |
| download | linux-28ee8b0912ca2ff68c2c03ff97bf1c22634c7942.tar.xz | |
crypto: marvell/cesa - irq balance
Balance the irqs of the marvell cesa driver over all
available cpus.
Currently all interrupts are handled by the first CPU.
From my testing with IPSec AES 256 SHA256
on my clearfog base with 2 Cores I get a 2x speed increase:
Before the patch: 26.74 Kpps
With the patch: 56.11 Kpps
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'crypto/xts.c')
0 files changed, 0 insertions, 0 deletions