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author | Magnus Damm <damm+renesas@opensource.se> | 2019-08-20 15:35:46 +0300 |
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committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2019-08-27 01:31:39 +0300 |
commit | 1be8c9fd2ac9ad730cf537b8909f66c357866c5d (patch) | |
tree | ae380b4907c20159b2a3198a5f2c3b1fa6bc9bac /crypto | |
parent | 53933bc3a69e0f07a1af2fea16fda9c816ffcf87 (diff) | |
download | linux-1be8c9fd2ac9ad730cf537b8909f66c357866c5d.tar.xz |
dt-bindings: timer: renesas, cmt: Update R-Car Gen3 CMT1 usage
The R-Car Gen3 SoCs so far come with a total for 4 on-chip CMT devices:
- CMT0
- CMT1
- CMT2
- CMT3
CMT0 includes two rather basic 32-bit timer channels. The rest of the on-chip
CMT devices support 48-bit counters and have 8 channels each.
Based on the data sheet information "CMT2/3 are exactly same as CMT1"
it seems that CMT2 and CMT3 now use the CMT1 compat string in the DTSI.
Clarify this in the DT binding documentation by describing R-Car Gen3 and
RZ/G2 CMT1 as "48-bit CMT devices".
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions