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author | Olga Kitaina <okitain@gmail.com> | 2022-06-28 18:48:24 +0300 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-08-21 16:16:16 +0300 |
commit | 04c9d23ac352fb006fc013fca1b9690fe817108e (patch) | |
tree | e86b5d7cc438a0304ced1f0fac75c07a316da26a /drivers/base/topology.c | |
parent | dc0e4a10b49d0d9569cc5fb5a4edf53e795994ba (diff) | |
download | linux-04c9d23ac352fb006fc013fca1b9690fe817108e.tar.xz |
mtd: rawnand: arasan: Fix clock rate in NV-DDR
[ Upstream commit e16eceea863b417fd328588b1be1a79de0bc937f ]
According to the Arasan NAND controller spec, the flash clock rate for SDR
must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
which would result in incorrect behavior for NV-DDR modes 0-4.
The appropriate clock rate can be calculated from the NV-DDR timing
parameters as 1/tCK, or for rates measured in picoseconds,
10^12 / nand_nvddr_timings->tCK_min.
Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: stable@vger.kernel.org # 5.8+
Signed-off-by: Olga Kitaina <okitain@gmail.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220628154824.12222-3-amit.kumar-mahapatra@xilinx.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/base/topology.c')
0 files changed, 0 insertions, 0 deletions