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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-25 02:42:43 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-25 02:42:43 +0300
commit6467a71c56934251f3c917bd4386387c2a97b41e (patch)
tree09f930fda8c6c555d488971d76e728846be55650 /drivers/char
parent18020a0d8cccad0d3642219d6aef789420c04c1f (diff)
parent6e6c822868f113dabe3c33bdd91e883cc28fa11b (diff)
downloadlinux-6467a71c56934251f3c917bd4386387c2a97b41e.tar.xz
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Stop trying to use ACPI lid status to determine LVDS connection. drm/intel: fix up set_tiling for untiled->tiled transition drm/i915: Set up the documented clock gating on Sandybridge and Ironlake. agp/intel: Don't do the chipset flush on Sandybridge. agp/intel: Respect the GTT size on Sandybridge for scratch page setup. drm/i915: fix small leak on overlay error path drm/i915: Avoid NULL deref in get_pages() unwind after error. drm/i915: Fix check with IS_GEN6 drivers/gpu/drm/i915/intel_bios.c: fix continuation line formats drm/i915: Enable VS timer dispatch. drm/i915: Rename FBC_C3_IDLE to FBC_CTL_C3_IDLE to match other registers drm/i915: remove an unnecessary wait_request() drm/i915: Don't bother with the BKL for GEM ioctls.
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-agp.c34
1 files changed, 31 insertions, 3 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index a3e10dc7cc25..b78d5c381efe 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -97,6 +97,9 @@ EXPORT_SYMBOL(intel_agp_enabled);
#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
+#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
+
#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
@@ -107,8 +110,7 @@ EXPORT_SYMBOL(intel_agp_enabled);
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
- agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
- agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
+ IS_SNB)
extern int agp_memory_reserved;
@@ -175,6 +177,10 @@ extern int agp_memory_reserved;
#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
+#define SNB_GTT_SIZE_0M (0 << 8)
+#define SNB_GTT_SIZE_1M (1 << 8)
+#define SNB_GTT_SIZE_2M (2 << 8)
+#define SNB_GTT_SIZE_MASK (3 << 8)
static const struct aper_size_info_fixed intel_i810_sizes[] =
{
@@ -1200,6 +1206,9 @@ static void intel_i9xx_setup_flush(void)
if (intel_private.ifp_resource.start)
return;
+ if (IS_SNB)
+ return;
+
/* setup a resource for this object */
intel_private.ifp_resource.name = "Intel Flush Page";
intel_private.ifp_resource.flags = IORESOURCE_MEM;
@@ -1438,6 +1447,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
{
+ u16 snb_gmch_ctl;
+
switch (agp_bridge->dev->device) {
case PCI_DEVICE_ID_INTEL_GM45_HB:
case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
@@ -1449,9 +1460,26 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
+ *gtt_offset = *gtt_size = MB(2);
+ break;
case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
- *gtt_offset = *gtt_size = MB(2);
+ *gtt_offset = MB(2);
+
+ pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+ switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
+ default:
+ case SNB_GTT_SIZE_0M:
+ printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
+ *gtt_size = MB(0);
+ break;
+ case SNB_GTT_SIZE_1M:
+ *gtt_size = MB(1);
+ break;
+ case SNB_GTT_SIZE_2M:
+ *gtt_size = MB(2);
+ break;
+ }
break;
default:
*gtt_offset = *gtt_size = KB(512);