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| author | Stephen Boyd <sboyd@kernel.org> | 2023-10-14 01:04:19 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-10-14 01:04:19 +0300 |
| commit | c3f187461f090edffcb556d89a2726a522d69ae9 (patch) | |
| tree | 0c9f96ba77b1edf1eafbc7ca21b1bd4248c17146 /drivers/clk/Kconfig | |
| parent | 295213436529502d679e521217b778ca11b5c2b1 (diff) | |
| parent | 4bce4bedbe6daa54cf701184601f913a0c00bb1c (diff) | |
| download | linux-c3f187461f090edffcb556d89a2726a522d69ae9.tar.xz | |
Merge tag 'renesas-clk-for-v6.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pulll more Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the RZ/G3S (R9A08G045) SoC
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
clk: renesas: Add minimal boot support for RZ/G3S SoC
clk: renesas: rzg2l: Add divider clock for RZ/G3S
clk: renesas: rzg2l: Refactor SD mux driver
clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
clk: renesas: rzg2l: Add struct clk_hw_data
clk: renesas: rzg2l: Add support for RZ/G3S PLL
clk: renesas: rzg2l: Remove critical area
clk: renesas: rzg2l: Fix computation formula
clk: renesas: rzg2l: Trust value returned by hardware
clk: renesas: rzg2l: Lock around writes to mux register
clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
clk: renesas: rcar-gen3: Extend SDnH divider table
dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
Diffstat (limited to 'drivers/clk/Kconfig')
0 files changed, 0 insertions, 0 deletions