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authorRonald Wahl <rwahl@gmx.de>2018-10-10 16:54:54 +0300
committerStephen Boyd <sboyd@kernel.org>2018-10-17 00:49:39 +0300
commit0f5cb0e6225cae2f029944cb8c74617aab6ddd49 (patch)
tree9f728cd6f6bb0aa004c3560327beb7dc33f6ac61 /drivers/clk/at91/clk-pll.c
parent5b394b2ddf0347bef56e50c69a58773c94343ff3 (diff)
downloadlinux-0f5cb0e6225cae2f029944cb8c74617aab6ddd49.tar.xz
clk: at91: Fix division by zero in PLL recalc_rate()
Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL and DIV values") removed a check that prevents a division by zero. This now causes a stacktrace when booting the kernel on a at91 platform if the PLL DIV register contains zero. This commit reintroduces this check. Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...") Cc: <stable@vger.kernel.org> Signed-off-by: Ronald Wahl <rwahl@gmx.de> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91/clk-pll.c')
-rw-r--r--drivers/clk/at91/clk-pll.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 72b6091eb7b9..dc7fbc796cb6 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -133,6 +133,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
{
struct clk_pll *pll = to_clk_pll(hw);
+ if (!pll->div || !pll->mul)
+ return 0;
+
return (parent_rate / pll->div) * (pll->mul + 1);
}