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authorBoris BREZILLON <b.brezillon@overkiz.com>2013-10-11 12:51:23 +0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2013-12-02 18:31:23 +0400
commite442d234405ad75e2d3d2baf15b364ee2c3573c9 (patch)
tree3aa5e2666bf5fccf0e4c61cf50030c839d7ef1b7 /drivers/clk/at91/clk-pll.c
parent1a748d2bc5061b72588013a720645661345c0e65 (diff)
downloadlinux-e442d234405ad75e2d3d2baf15b364ee2c3573c9.tar.xz
clk: at91: add PMC master clock
This patch adds new at91 master clock implementation using common clk framework. The master clock layout describe the MCKR register layout. There are 2 master clock layouts: - at91rm9200 - at91sam9x5 Master clocks are given characteristics: - min/max clock output rate These characteristics are checked during rate change to avoid over/underclocking. These characteristics are described in atmel's SoC datasheet in "Electrical Characteristics" paragraph. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'drivers/clk/at91/clk-pll.c')
-rw-r--r--drivers/clk/at91/clk-pll.c10
1 files changed, 2 insertions, 8 deletions
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 5e23ee4ce387..cf6ed023504c 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -80,6 +80,8 @@ static int clk_pll_prepare(struct clk_hw *hw)
struct clk_pll *pll = to_clk_pll(hw);
struct at91_pmc *pmc = pll->pmc;
const struct clk_pll_layout *layout = pll->layout;
+ const struct clk_pll_characteristics *characteristics =
+ pll->characteristics;
u8 id = pll->id;
u32 mask = PLL_STATUS_MASK(id);
int offset = PLL_REG(id);
@@ -269,18 +271,10 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pll *pll = to_clk_pll(hw);
- struct at91_pmc *pmc = pll->pmc;
- const struct clk_pll_layout *layout = pll->layout;
- const struct clk_pll_characteristics *characteristics =
- pll->characteristics;
- u8 id = pll->id;
- int offset = PLL_REG(id);
long ret;
u32 div;
u32 mul;
u32 index;
- u32 tmp;
- u8 out = 0;
ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
&div, &mul, &index);