diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-10-11 14:27:05 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-10-27 04:27:41 +0300 |
| commit | 36971566ea7a519bcde1830f39b6aa37c34e0fb4 (patch) | |
| tree | 5e2bc834ef97c1b35b5ecce1cf7a01bc4c377cba /drivers/clk/at91/clk-programmable.c | |
| parent | c405f5c15e9f6094f2fa1658e73e56f3058e2122 (diff) | |
| download | linux-36971566ea7a519bcde1830f39b6aa37c34e0fb4.tar.xz | |
clk: at91: re-factor clocks suspend/resume
SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where
most of the SoC's components are powered off (including PMC). Resuming
from this mode is done with the help of bootloader. Peripherals are not
aware of the power saving mode thus most of them are disabling clocks in
proper suspend API and re-enable them in resume API without taking into
account the previously setup rate. Moreover some of the peripherals are
acting as wakeup sources and are not disabling the clocks in this
scenario, when suspending. Since backup mode cuts the power for
peripherals, in resume part these clocks needs to be re-configured.
The initial PMC suspend/resume code was designed only for SAMA5D2's PMC
(as it was the only one supporting backup mode). SAMA7G supports also
backup mode and its PMC is different (few new functionalities, different
registers offsets, different offsets in registers for each
functionalities). To address both SAMA5D2 and SAMA7G5 PMC add
.save_context()/.resume_context() support to each clocks driver and call
this from PMC driver.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91/clk-programmable.c')
| -rw-r--r-- | drivers/clk/at91/clk-programmable.c | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index fcf8f6a1c2c6..6c4b259d31d3 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -24,6 +24,7 @@ struct clk_programmable { u32 *mux_table; u8 id; const struct clk_programmable_layout *layout; + struct at91_clk_pms pms; }; #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw) @@ -177,12 +178,38 @@ static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int clk_programmable_save_context(struct clk_hw *hw) +{ + struct clk_programmable *prog = to_clk_programmable(hw); + struct clk_hw *parent_hw = clk_hw_get_parent(hw); + + prog->pms.parent = clk_programmable_get_parent(hw); + prog->pms.parent_rate = clk_hw_get_rate(parent_hw); + prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate); + + return 0; +} + +static void clk_programmable_restore_context(struct clk_hw *hw) +{ + struct clk_programmable *prog = to_clk_programmable(hw); + int ret; + + ret = clk_programmable_set_parent(hw, prog->pms.parent); + if (ret) + return; + + clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate); +} + static const struct clk_ops programmable_ops = { .recalc_rate = clk_programmable_recalc_rate, .determine_rate = clk_programmable_determine_rate, .get_parent = clk_programmable_get_parent, .set_parent = clk_programmable_set_parent, .set_rate = clk_programmable_set_rate, + .save_context = clk_programmable_save_context, + .restore_context = clk_programmable_restore_context, }; struct clk_hw * __init @@ -221,8 +248,6 @@ at91_clk_register_programmable(struct regmap *regmap, if (ret) { kfree(prog); hw = ERR_PTR(ret); - } else { - pmc_register_pck(id); } return hw; |