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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2014-09-15 20:15:53 +0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-09-22 13:38:59 +0400
commitbcc5fd49a0fda5abc22057f65b318788ccb5d2ad (patch)
treeedf97c273ea66306e5a6fdd81e6c5a78d31e8873 /drivers/clk/at91/pmc.c
parent5db722eeba0051c68e638114f6720e715b03cd2c (diff)
downloadlinux-bcc5fd49a0fda5abc22057f65b318788ccb5d2ad.tar.xz
clk: at91: add a driver for the h32mx clock
Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'drivers/clk/at91/pmc.c')
-rw-r--r--drivers/clk/at91/pmc.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 524196bb35a5..386999b4f8eb 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -337,6 +337,12 @@ static const struct of_device_id pmc_clk_ids[] __initconst = {
.data = of_at91sam9x5_clk_smd_setup,
},
#endif
+#if defined(CONFIG_HAVE_AT91_H32MX)
+ {
+ .compatible = "atmel,sama5d4-clk-h32mx",
+ .data = of_sama5d4_clk_h32mx_setup,
+ },
+#endif
{ /*sentinel*/ }
};