diff options
author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2019-04-02 15:50:54 +0300 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-25 22:34:06 +0300 |
commit | a436c2a447e59740e8bc5c604abac33419099673 (patch) | |
tree | dcbabdd4516f54caeb5bd438a3b3c6c1459fa215 /drivers/clk/at91/pmc.h | |
parent | e5be537064dd36129a724c65820e5fc2daebd5f4 (diff) | |
download | linux-a436c2a447e59740e8bc5c604abac33419099673.tar.xz |
clk: at91: add sam9x60 PLL driver
The PLLs on the sam9x60 (PLLA and USB PLL) use a different register set and
programming model than the previous SoCs.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91/pmc.h')
-rw-r--r-- | drivers/clk/at91/pmc.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 4a30c20f17f1..fb9e9c4cdc8d 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -69,6 +69,7 @@ struct clk_pll_characteristics { struct clk_range *output; u16 *icpll; u8 *out; + u8 upll : 1; }; struct clk_programmable_layout { @@ -170,6 +171,11 @@ at91_clk_register_plldiv(struct regmap *regmap, const char *name, const char *parent_name); struct clk_hw * __init +sam9x60_clk_register_pll(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics); + +struct clk_hw * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_programmable_layout *layout); |