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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2020-03-11 16:41:13 +0300
committerStephen Boyd <sboyd@kernel.org>2020-05-29 07:06:39 +0300
commit907f9291f937463c27e5ca9cb5f1d8eedf9a2738 (patch)
tree81d08faa17508d4a678aef95d518dcfe3290f5bb /drivers/clk/clk-hsdk-pll.c
parent8f3d9f354286745c751374f5f1fcafee6b3f3136 (diff)
downloadlinux-907f9291f937463c27e5ca9cb5f1d8eedf9a2738.tar.xz
CLK: HSDK: CGU: check if PLL is bypassed first
If PLL is bypassed the EN (enable) bit has no effect on output clock. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lkml.kernel.org/r/20200311134115.13257-2-Eugeniy.Paltsev@synopsys.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-hsdk-pll.c')
-rw-r--r--drivers/clk/clk-hsdk-pll.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 97d1e8c35b71..b47a559f3528 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -172,14 +172,14 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
dev_dbg(clk->dev, "current configuration: %#x\n", val);
- /* Check if PLL is disabled */
- if (val & CGU_PLL_CTRL_PD)
- return 0;
-
/* Check if PLL is bypassed */
if (val & CGU_PLL_CTRL_BYPASS)
return parent_rate;
+ /* Check if PLL is disabled */
+ if (val & CGU_PLL_CTRL_PD)
+ return 0;
+
/* input divider = reg.idiv + 1 */
idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
/* fb divider = 2*(reg.fbdiv + 1) */