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| author | Jay Buddhabhatti <jay.buddhabhatti@amd.com> | 2023-11-29 14:29:16 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-12-17 04:20:14 +0300 |
| commit | 1fe15be1fb613534ecbac5f8c3f8744f757d237d (patch) | |
| tree | 52a8ae51845764d8454a11b75f4565950cf156ad /drivers/clk/clk-versaclock3.c | |
| parent | b782921ddd7f84f524723090377903f399fdbbcb (diff) | |
| download | linux-1fe15be1fb613534ecbac5f8c3f8744f757d237d.tar.xz | |
drivers: clk: zynqmp: update divider round rate logic
Currently zynqmp divider round rate is considering single parent and
calculating rate and parent rate accordingly. But if divider clock flag
is set to SET_RATE_PARENT then its not trying to traverse through all
parent rate and not selecting best parent rate from that. So use common
divider_round_rate() which is traversing through all clock parents and
its rate and calculating proper parent rate.
Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Link: https://lore.kernel.org/r/20231129112916.23125-3-jay.buddhabhatti@amd.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-versaclock3.c')
0 files changed, 0 insertions, 0 deletions