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authorShawn Lin <shawn.lin@rock-chips.com>2018-03-08 09:49:41 +0300
committerMichael Turquette <mturquette@baylibre.com>2018-03-12 04:21:19 +0300
commit7f95beea36089918335eb1810ddd7ba8cf9d09cc (patch)
treeb47461069098a6da89d660de586ff96fc00c47ed /drivers/clk/clk.c
parent7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff)
downloadlinux-7f95beea36089918335eb1810ddd7ba8cf9d09cc.tar.xz
clk: update cached phase to respect the fact when setting phase
It's found that the final phase set by driver doesn't match that of the output from clk_summary: dwmmc_rockchip fe310000.dwmmc: Successfully tuned phase to 346 mmc0: new ultra high speed SDR104 SDIO card at address 0001 cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample sdio_sample 0 1 0 50000000 0 0 It seems the cached core->phase isn't updated after the clk was registered. So fix this issue by updating the core->phase if setting phase successfully. Fixes: 9e4d04adeb1a ("clk: add clk_core_set_phase_nolock function") Cc: Stable <stable@vger.kernel.org> Cc: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/clk.c')
-rw-r--r--drivers/clk/clk.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 0f686a9dac3e..617e56268b18 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2309,8 +2309,11 @@ static int clk_core_set_phase_nolock(struct clk_core *core, int degrees)
trace_clk_set_phase(core, degrees);
- if (core->ops->set_phase)
+ if (core->ops->set_phase) {
ret = core->ops->set_phase(core->hw, degrees);
+ if (!ret)
+ core->phase = degrees;
+ }
trace_clk_set_phase_complete(core, degrees);