diff options
| author | David Lechner <david@lechnology.com> | 2018-05-25 21:11:47 +0300 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2018-05-30 22:48:35 +0300 |
| commit | 76c9dd9dbd6459f1faf2b10351eb3d3f90255fa1 (patch) | |
| tree | 48053e2359e7fe36ef488bdbf01a3429ba104964 /drivers/clk/davinci/pll-dm365.c | |
| parent | 9c39fc1fe87a5f60f0103afbbcf0d8eaedc28ab7 (diff) | |
| download | linux-76c9dd9dbd6459f1faf2b10351eb3d3f90255fa1.tar.xz | |
clk: davinci: pll: allow dev == NULL
This modifies the TI Davinci PLL clock driver to allow for the case
when dev == NULL. On some (most) SoCs that use this driver, the PLL
clock needs to be registered during early boot because it is used
for clocksource/clkevent and there will be no platform device available.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com
Diffstat (limited to 'drivers/clk/davinci/pll-dm365.c')
| -rw-r--r-- | drivers/clk/davinci/pll-dm365.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/clk/davinci/pll-dm365.c b/drivers/clk/davinci/pll-dm365.c index 5f8d9f42d0f3..2d29712753a3 100644 --- a/drivers/clk/davinci/pll-dm365.c +++ b/drivers/clk/davinci/pll-dm365.c @@ -7,6 +7,7 @@ #include <linux/bitops.h> #include <linux/clkdev.h> +#include <linux/clk/davinci.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/types.h> @@ -56,11 +57,11 @@ static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = { .ocsrc_mask = BIT(4), }; -int dm365_pll1_init(struct device *dev, void __iomem *base) +int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; - davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base); + davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc"); @@ -119,11 +120,11 @@ static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = { .ocsrc_mask = BIT(4), }; -int dm365_pll2_init(struct device *dev, void __iomem *base) +int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; - davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base); + davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip); davinci_pll_sysclk_register(dev, &pll2_sysclk1, base); |