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authorPaul Cercueil <paul@crapouillou.net>2019-03-19 17:05:36 +0300
committerStephen Boyd <sboyd@kernel.org>2019-04-11 23:41:11 +0300
commiteaa9558d35aee594c9658d92852e537a0fb897d7 (patch)
treefa8c13bddb58ebfaea2be50daf2a5f5c51da4057 /drivers/clk/ingenic
parent93dc07f8b089ee073075c22873ab707225e192b5 (diff)
downloadlinux-eaa9558d35aee594c9658d92852e537a0fb897d7.tar.xz
clk: ingenic: jz4725b: Add UDC PHY clock
Add clock for the USB Device Controller PHY. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic')
-rw-r--r--drivers/clk/ingenic/jz4725b-cgu.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 584ff4ff81c7..8901ea0295b7 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -205,6 +205,12 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
.mux = { CGU_REG_OPCR, 2, 1},
},
+
+ [JZ4725B_CLK_UDC_PHY] = {
+ "udc_phy", CGU_CLK_GATE,
+ .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+ .gate = { CGU_REG_OPCR, 6, true },
+ },
};
static void __init jz4725b_cgu_init(struct device_node *np)