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authorJohnson Wang <johnson.wang@mediatek.com>2022-11-21 15:29:56 +0300
committerChen-Yu Tsai <wenst@chromium.org>2022-11-29 09:43:07 +0300
commitd7964de8a8ea800910fdd4e365c42a9e7d5c54aa (patch)
tree96fb0279f6b4cee4b4dd42474b3811017139d807 /drivers/clk/mediatek/Makefile
parentcfcefe36bf939107eeba7b1114e3d82e31f92893 (diff)
downloadlinux-d7964de8a8ea800910fdd4e365c42a9e7d5c54aa.tar.xz
clk: mediatek: Add new clock driver to handle FHCTL hardware
To implement frequency hopping and spread spectrum clocking function, we introduce new clock type and APIs to handle FHCTL hardware. Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221121122957.21611-4-johnson.wang@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Diffstat (limited to 'drivers/clk/mediatek/Makefile')
-rw-r--r--drivers/clk/mediatek/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index ea3b73240303..e24080fd6e7f 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
+obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o