diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-02-06 13:00:59 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-03-13 21:46:23 +0300 |
| commit | 8da312d6574c7b3f58ee8dbc85afa392224b5470 (patch) | |
| tree | 56c7b12ebeb82ba32cdb0b02cf76b86b0589670e /drivers/clk/mediatek/clk-fhctl.c | |
| parent | fe15c26ee26efa11741a7b632e9f23b01aca4cc6 (diff) | |
| download | linux-8da312d6574c7b3f58ee8dbc85afa392224b5470.tar.xz | |
clk: mediatek: fhctl: Add support for older fhctl register layout
The Frequency Hopping Controller (FHCTL) seems to have different
versions, as it has a slightly different register layout on some
older SoCs like MT6795, MT8173, MT8183 (and others).
This driver is indeed compatible with at least some of those older
IP revisions, so all we need to do is to add a way to select the
right register layout at registration time.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-2-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-fhctl.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-fhctl.c | 26 |
1 files changed, 23 insertions, 3 deletions
diff --git a/drivers/clk/mediatek/clk-fhctl.c b/drivers/clk/mediatek/clk-fhctl.c index 4f271acef5fe..45e4842cbf04 100644 --- a/drivers/clk/mediatek/clk-fhctl.c +++ b/drivers/clk/mediatek/clk-fhctl.c @@ -14,7 +14,20 @@ #define PERCENT_TO_DDSLMT(dds, percent_m10) \ ((((dds) * (percent_m10)) >> 5) / 100) -static const struct fhctl_offset fhctl_offset = { +const struct fhctl_offset fhctl_offset_v1 = { + .offset_hp_en = 0x0, + .offset_clk_con = 0x4, + .offset_rst_con = 0x8, + .offset_slope0 = 0xc, + .offset_slope1 = 0x10, + .offset_cfg = 0x0, + .offset_updnlmt = 0x4, + .offset_dds = 0x8, + .offset_dvfs = 0xc, + .offset_mon = 0x10, +}; + +const struct fhctl_offset fhctl_offset_v2 = { .offset_hp_en = 0x0, .offset_clk_con = 0x8, .offset_rst_con = 0xc, @@ -27,9 +40,16 @@ static const struct fhctl_offset fhctl_offset = { .offset_mon = 0x10, }; -const struct fhctl_offset *fhctl_get_offset_table(void) +const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v) { - return &fhctl_offset; + switch (v) { + case FHCTL_PLLFH_V1: + return &fhctl_offset_v1; + case FHCTL_PLLFH_V2: + return &fhctl_offset_v2; + default: + return ERR_PTR(-EINVAL); + }; } static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs, |