diff options
| author | Johnson Wang <johnson.wang@mediatek.com> | 2022-11-21 15:29:56 +0300 |
|---|---|---|
| committer | Chen-Yu Tsai <wenst@chromium.org> | 2022-11-29 09:43:07 +0300 |
| commit | d7964de8a8ea800910fdd4e365c42a9e7d5c54aa (patch) | |
| tree | 96fb0279f6b4cee4b4dd42474b3811017139d807 /drivers/clk/mediatek/clk-fhctl.h | |
| parent | cfcefe36bf939107eeba7b1114e3d82e31f92893 (diff) | |
| download | linux-d7964de8a8ea800910fdd4e365c42a9e7d5c54aa.tar.xz | |
clk: mediatek: Add new clock driver to handle FHCTL hardware
To implement frequency hopping and spread spectrum clocking
function, we introduce new clock type and APIs to handle
FHCTL hardware.
Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221121122957.21611-4-johnson.wang@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-fhctl.h')
| -rw-r--r-- | drivers/clk/mediatek/clk-fhctl.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-fhctl.h b/drivers/clk/mediatek/clk-fhctl.h new file mode 100644 index 000000000000..51275febf086 --- /dev/null +++ b/drivers/clk/mediatek/clk-fhctl.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Edward-JW Yang <edward-jw.yang@mediatek.com> + */ + +#ifndef __CLK_FHCTL_H +#define __CLK_FHCTL_H + +struct fhctl_offset { + u32 offset_hp_en; + u32 offset_clk_con; + u32 offset_rst_con; + u32 offset_slope0; + u32 offset_slope1; + u32 offset_cfg; + u32 offset_updnlmt; + u32 offset_dds; + u32 offset_dvfs; + u32 offset_mon; +}; +const struct fhctl_offset *fhctl_get_offset_table(void); +const struct fh_operation *fhctl_get_ops(void); +void fhctl_hw_init(struct mtk_fh *fh); + +#endif |