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author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-03-06 17:05:10 +0300 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2023-03-13 21:50:15 +0300 |
commit | 3f37ba7cc385ba07762ffcd7ac38af8c0f84dd3e (patch) | |
tree | 08d2177eae36e23b608b9c0e14960614b8d3cc36 /drivers/clk/mediatek/clk-mt2701-g3d.c | |
parent | 2f140dabfe49745582226af4b4c371f4b248e7cf (diff) | |
download | linux-3f37ba7cc385ba07762ffcd7ac38af8c0f84dd3e.tar.xz |
clk: mediatek: mt8183: Convert all remaining clocks to common probe
Switch to mtk_clk_simple_{probe,remove}() for infracfg and topckgen
clocks on MT8183 to allow full module build for clock drivers.
Differently from other MediaTek clock drivers, it was necessary to
change the name of the `clk13m` clock, as that is already declared
in the SoC's devicetree as a "fixed-factor-clock" (with the same
name) and redeclaring it here would obviously fail to register the
entire clock controller; this clock wasn't dropped only to retain
compatibility with older devicetrees
As a note, the `clk13m` clock is not mentioned in any parent names
array(s) as the correct one (csw_f26m_d2) is already used in place
of that.
Thanks to the conversion, more error handling was added to the clocks
registration.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-22-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt2701-g3d.c')
0 files changed, 0 insertions, 0 deletions