diff options
author | Chun-Jie Chen <chun-jie.chen@mediatek.com> | 2022-05-13 10:36:21 +0300 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2022-05-19 03:42:22 +0300 |
commit | e1fd35f5cdffea714f7a285a1eb68863c72acb4e (patch) | |
tree | a4f1f85a46641ecb19c2f4616f9eee87305c37d3 /drivers/clk/mediatek/clk-mt7622.c | |
parent | 544e9ec70f9335b07498319a2dacc6732a73850b (diff) | |
download | linux-e1fd35f5cdffea714f7a285a1eb68863c72acb4e.tar.xz |
clk: mediatek: use en_mask as a pure div_en_mask
We no longer allow en_mask to be a combination of
pll_en_bit and div_en_mask, so remove pll_en_bit(bit0)
from en_mask to make en_mask a pure en_mask that only
used for pll dividers.
This commit continues the work done in commit 7cc4e1bbe300
("clk: mediatek: Fix asymmetrical PLL enable and disable
control") and commit f384c44754b7 ("clk: mediatek:
Add configurable enable control to mtk_pll_data") to
clean up en_mask(bit0) default setting.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com>
Link: https://lore.kernel.org/r/20220513073621.12923-1-mandyjh.liu@mediatek.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt7622.c')
-rw-r--r-- | drivers/clk/mediatek/clk-mt7622.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 0e1fb30a1e98..7543c6de01a0 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -329,23 +329,23 @@ static const struct mtk_gate_regs peri1_cg_regs = { }; static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0, PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001, + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0, HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), - PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001, + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0, HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), - PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001, + PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0, 0, 21, 0x0300, 1, 0, 0x0304, 0), - PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001, + PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0, 0, 21, 0x0314, 1, 0, 0x0318, 0), - PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001, + PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0, 0, 31, 0x0324, 1, 0, 0x0328, 0), - PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001, + PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0, 0, 31, 0x0334, 1, 0, 0x0338, 0), - PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001, + PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0, 0, 21, 0x0344, 1, 0, 0x0348, 0), - PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001, + PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0, 0, 21, 0x0358, 1, 0, 0x035C, 0), }; |