diff options
| author | yong.liang <yong.liang@mediatek.com> | 2019-07-26 10:01:35 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-08-08 18:19:21 +0300 |
| commit | 64ebb57a3df6c7126532f8acd22b0612867ad3e0 (patch) | |
| tree | ab146bb33776d89c3f3cb165bde12b66b83ffb91 /drivers/clk/mediatek/clk-mt8183.c | |
| parent | 5f9e832c137075045d15cd6899ab0505cfb2ca4b (diff) | |
| download | linux-64ebb57a3df6c7126532f8acd22b0612867ad3e0.tar.xz | |
clk: reset: Modify reset-controller driver
Set reset signal by a register and
clear reset signal by another register for 8183.
Signed-off-by: yong.liang <yong.liang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8183.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8183.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 1aa5f4059251..94bbadc0d259 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -17,6 +17,9 @@ #include <dt-bindings/clock/mt8183-clk.h> +/* Infra global controller reset set register */ +#define INFRA_RST0_SET_OFFSET 0x120 + static DEFINE_SPINLOCK(mt8183_clk_lock); static const struct mtk_fixed_clk top_fixed_clks[] = { @@ -1185,13 +1188,24 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; + int r; clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); - return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + dev_err(&pdev->dev, + "%s(): could not register clock provider: %d\n", + __func__, r); + return r; + } + + mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET); + + return r; } static int clk_mt8183_mcu_probe(struct platform_device *pdev) |