summaryrefslogtreecommitdiff
path: root/drivers/clk/mediatek/clk-mt8195-infra_ao.c
diff options
context:
space:
mode:
authorRex-BC Chen <rex-bc.chen@mediatek.com>2022-05-23 12:33:41 +0300
committerStephen Boyd <sboyd@kernel.org>2022-06-16 03:24:13 +0300
commita0bc8ae5a0d7c79e376f400d989698194c6af7a1 (patch)
treeb057d758695933af48021a77ca075f81230a92e5 /drivers/clk/mediatek/clk-mt8195-infra_ao.c
parentfb91526b5fb04133799bc708661b467226caa032 (diff)
downloadlinux-a0bc8ae5a0d7c79e376f400d989698194c6af7a1.tar.xz
clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
The infra_ao reset is needed for MT8192 and MT8195. - Add mtk_clk_rst_desc for MT8192 and MT8195 - Add register reset controller function for MT8192 infra_ao. - Move definition of infra reset from cl-mt8183.c to reset.h because it's the same definition with MT8192 and MT8195. - Add new definition of infra reset_4 for MT8192 and MT8195. - Add infra_ao_idx_map for MT8192 and MT8195. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-15-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8195-infra_ao.c')
-rw-r--r--drivers/clk/mediatek/clk-mt8195-infra_ao.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 8ebe3b9415c4..97657f255618 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -7,6 +7,7 @@
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/reset/mt8195-resets.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
@@ -182,9 +183,32 @@ static const struct mtk_gate infra_ao_clks[] = {
GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
};
+static u16 infra_ao_rst_ofs[] = {
+ INFRA_RST0_SET_OFFSET,
+ INFRA_RST1_SET_OFFSET,
+ INFRA_RST2_SET_OFFSET,
+ INFRA_RST3_SET_OFFSET,
+ INFRA_RST4_SET_OFFSET,
+};
+
+static u16 infra_ao_idx_map[] = {
+ [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
+ [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
+ [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
+};
+
+static struct mtk_clk_rst_desc infra_ao_rst_desc = {
+ .version = MTK_RST_SET_CLR,
+ .rst_bank_ofs = infra_ao_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
+ .rst_idx_map = infra_ao_idx_map,
+ .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
+};
+
static const struct mtk_clk_desc infra_ao_desc = {
.clks = infra_ao_clks,
.num_clks = ARRAY_SIZE(infra_ao_clks),
+ .rst_desc = &infra_ao_rst_desc,
};
static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {