diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-05-16 16:52:04 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-06-13 04:20:04 +0300 |
| commit | 1775790eff4a8fa885db189c75f4ce98e7a6a1dc (patch) | |
| tree | 4e686957c83c0fe4580e3d5192b8d7adee8d088e /drivers/clk/mediatek/clk-mt8195-topckgen.c | |
| parent | 5f17cdb06e2a90b8318120933afe46b9fb01c129 (diff) | |
| download | linux-1775790eff4a8fa885db189c75f4ce98e7a6a1dc.tar.xz | |
clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag
The clk-mux driver was forcing the CLK_SET_RATE_PARENT flag even for
the GATE_CLK_SET_UPD_FLAGS() macro, as in mtk_clk_register_mux() the
flag was unconditionally added.
In preparation for a change on MSDC clock muxes, stop forcing this
flag and, where necessary, update clock drivers to add it so that
with this commit we introduce no functional changes for the currently
supported SoCs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20230516135205.372951-2-angelogioacchino.delregno@collabora.com
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8195-topckgen.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8195-topckgen.c | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 3c2174c3e742..3acbd1c907ab 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -862,13 +862,17 @@ static const struct mtk_mux top_mtk_muxes[] = { * top_spm and top_scp are main clocks in always-on co-processor. */ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", - axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL), + axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", - spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL), + spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", - scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, CLK_IS_CRITICAL), + scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", - bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL), + bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), /* CLK_CFG_1 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp", vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4), @@ -951,7 +955,8 @@ static const struct mtk_mux top_mtk_muxes[] = { MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb", atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu", - pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL), + pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp", dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), /* CLK_CFG_10 */ @@ -1020,7 +1025,8 @@ static const struct mtk_mux top_mtk_muxes[] = { MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm", pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", - mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, CLK_IS_CRITICAL), + mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), /* * CLK_CFG_17 * top_dvfsrc is for internal DVFS usage, should not be handled by Linux. @@ -1030,7 +1036,8 @@ static const struct mtk_mux top_mtk_muxes[] = { MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst", spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", - dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, CLK_IS_CRITICAL), + dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl", tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7), /* CLK_CFG_18 */ @@ -1141,11 +1148,14 @@ static const struct mtk_mux top_mtk_muxes[] = { MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref", dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", - ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, CLK_IS_CRITICAL), + ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core", - ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, CLK_IS_CRITICAL), + ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", - srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL), + srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), /* * the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled * by Linux. |