diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2019-03-05 08:05:44 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-11 23:20:16 +0300 |
| commit | 23fe31dedb7b1836cc23666afc1a9c67ed7de775 (patch) | |
| tree | 24ba1d4b58213f552c8679fff0278fb261da5db4 /drivers/clk/mediatek/clk-mtk.h | |
| parent | d90240bc073eccec5fffa80e7038460350c6f073 (diff) | |
| download | linux-23fe31dedb7b1836cc23666afc1a9c67ed7de775.tar.xz | |
clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
In previous MediaTek PLL design, it assumes the pcw change control
is always on the CON1 register.
However, the pcw change bit on MT8183 was moved onto CON0 because
the the PCW length of audio PLLs are extended to 32-bit.
Add configurable pcw_chg_reg to set the pcw change control register
address or using the default control register CON1 if without
setting in pll data.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.h')
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 9d53ee3dffd2..33ab1731482f 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -233,6 +233,7 @@ struct mtk_pll_data { int pcwibits; uint32_t pcw_reg; int pcw_shift; + uint32_t pcw_chg_reg; const struct mtk_pll_div_table *div_table; const char *parent_name; }; |