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authorChen-Yu Tsai <wenst@chromium.org>2022-02-08 15:40:15 +0300
committerStephen Boyd <sboyd@kernel.org>2022-02-17 23:12:23 +0300
commit39691fb67b6a4f09f839650b09f3eb33fd7d4d91 (patch)
treed0a4215f248ee870282a22ce717090cabf81b87a /drivers/clk/mediatek/clk-mtk.h
parentdc46de49264e3b57f3b64927512bcd49a2c745ad (diff)
downloadlinux-39691fb67b6a4f09f839650b09f3eb33fd7d4d91.tar.xz
clk: mediatek: pll: Split definitions into separate header file
When the PLL type clk was implemented in the MediaTek clk driver library, the data structure definitions and function declaration were put in the common header file. Since it is its own type of clk, and not all platform clk drivers utilize it, having the definitions in the common header results in wasted cycles during compilation. Split out the related definitions and declarations into its own header file, and include that only in the platform clk drivers that need it. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220208124034.414635-13-wenst@chromium.org Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.h')
-rw-r--r--drivers/clk/mediatek/clk-mtk.h39
1 files changed, 0 insertions, 39 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index bdec7dc5e07a..168220f85489 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -179,45 +179,6 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
void mtk_free_clk_data(struct clk_onecell_data *clk_data);
-#define HAVE_RST_BAR BIT(0)
-#define PLL_AO BIT(1)
-
-struct mtk_pll_div_table {
- u32 div;
- unsigned long freq;
-};
-
-struct mtk_pll_data {
- int id;
- const char *name;
- u32 reg;
- u32 pwr_reg;
- u32 en_mask;
- u32 pd_reg;
- u32 tuner_reg;
- u32 tuner_en_reg;
- u8 tuner_en_bit;
- int pd_shift;
- unsigned int flags;
- const struct clk_ops *ops;
- u32 rst_bar_mask;
- unsigned long fmin;
- unsigned long fmax;
- int pcwbits;
- int pcwibits;
- u32 pcw_reg;
- int pcw_shift;
- u32 pcw_chg_reg;
- const struct mtk_pll_div_table *div_table;
- const char *parent_name;
- u32 en_reg;
- u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
-};
-
-void mtk_clk_register_plls(struct device_node *node,
- const struct mtk_pll_data *plls, int num_plls,
- struct clk_onecell_data *clk_data);
-
struct clk *mtk_clk_register_ref2usb_tx(const char *name,
const char *parent_name, void __iomem *reg);