diff options
| author | Chun-Jie Chen <chun-jie.chen@mediatek.com> | 2021-07-26 13:57:05 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-07-27 20:53:06 +0300 |
| commit | f384c44754b7de2eceb0789a8837a11b0a80cdba (patch) | |
| tree | 6be192414ea54af96b45195b576c5dd474a9d64f /drivers/clk/mediatek/clk-mtk.h | |
| parent | 7cc4e1bbe300c5cf610ece8eca6c6751b8bc74db (diff) | |
| download | linux-f384c44754b7de2eceb0789a8837a11b0a80cdba.tar.xz | |
clk: mediatek: Add configurable enable control to mtk_pll_data
In all MediaTek PLL design, bit0 of CON0 register is always
the enable bit.
However, there's a special case of usbpll on MT8192.
The enable bit of usbpll is moved to bit2 of other register.
Add configurable en_reg and pll_en_bit for enable control or
default 0 where pll data are static variables.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-8-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.h')
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.h | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index c3d6756b0c7e..31c7cb304508 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -213,13 +213,13 @@ struct mtk_pll_div_table { struct mtk_pll_data { int id; const char *name; - uint32_t reg; - uint32_t pwr_reg; - uint32_t en_mask; - uint32_t pd_reg; - uint32_t tuner_reg; - uint32_t tuner_en_reg; - uint8_t tuner_en_bit; + u32 reg; + u32 pwr_reg; + u32 en_mask; + u32 pd_reg; + u32 tuner_reg; + u32 tuner_en_reg; + u8 tuner_en_bit; int pd_shift; unsigned int flags; const struct clk_ops *ops; @@ -228,11 +228,13 @@ struct mtk_pll_data { unsigned long fmax; int pcwbits; int pcwibits; - uint32_t pcw_reg; + u32 pcw_reg; int pcw_shift; - uint32_t pcw_chg_reg; + u32 pcw_chg_reg; const struct mtk_pll_div_table *div_table; const char *parent_name; + u32 en_reg; + u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ }; void mtk_clk_register_plls(struct device_node *node, |