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| author | Sam Shih <sam.shih@mediatek.com> | 2023-12-18 00:50:07 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-01-04 02:55:19 +0300 |
| commit | d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 (patch) | |
| tree | 7f6edc3a36c29eefdb7458c3de837dda6c597b51 /drivers/clk/mediatek/clk-pll.h | |
| parent | afd36e9d91b0a840983b829a9e95407d8151f7e7 (diff) | |
| download | linux-d9bf944beaaad1890ad3fcb755c61e1c7e4c5630.tar.xz | |
clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
of the previously hardcoded PCW_CHG_MASK macro if set.
This will needed for clocks on the MT7988 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-pll.h')
| -rw-r--r-- | drivers/clk/mediatek/clk-pll.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index f17278ff15d7..285c8db958b3 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -48,6 +48,7 @@ struct mtk_pll_data { const char *parent_name; u32 en_reg; u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ + u8 pcw_chg_bit; }; /* |