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author | Rhyland Klein <rklein@nvidia.com> | 2015-06-19 00:28:18 +0300 |
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committer | Thierry Reding <treding@nvidia.com> | 2015-11-20 20:04:17 +0300 |
commit | dc37fec48314d942003a414a4bab38f4688f09a3 (patch) | |
tree | c86f780758af2b393dec44ebfc18f8e509014f12 /drivers/clk/mediatek | |
parent | 385f9adf625f706ea3db80f08d723bd0dd5d1b03 (diff) | |
download | linux-dc37fec48314d942003a414a4bab38f4688f09a3.tar.xz |
clk: tegra: periph: Add new periph clks and muxes for Tegra210
Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.
Tegra210 has some differences in the PLLP clock tree:
- Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO,
and PLLP_OUT_XUSB.
- PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO.
- PLLP_OUT4 is the child of PLLP_OUT_CPU.
Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210.
Including work by Andrew Bresticker <abrestic@chromium.org> and
Bill Huang <bilhuang@nvidia.com>.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions