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| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-01-19 18:55:27 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 11:49:23 +0300 |
| commit | 3c4fe763d64db93c0c8ec359cf394cfc491f91f3 (patch) | |
| tree | c9b149483bb2edd7f6b79e595365ed470ef5a54a /drivers/clk/meson/clk-pll.c | |
| parent | 69d92293274b3ae60c54271bf6e029e3d1d582e8 (diff) | |
| download | linux-3c4fe763d64db93c0c8ec359cf394cfc491f91f3.tar.xz | |
clk: meson: fix rate calculation of plls with a fractional part
The rate of the parent should not be multiplied by 2 when the pll has a
fractional part. This is making the rate calculation of the gxl_hdmi_pll
wrong (and others as well). This multiplication is specific
to the hdmi_pll of gxbb and is most likely due to a multiplier sitting
in front of this particular pll.
Add a fixed factor clock in front on the gxbb pll and remove this constant
from the calculation to fix the problem
Fixes: 4a47295144dd ("clk: meson: fractional pll support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clk-pll.c')
| -rw-r--r-- | drivers/clk/meson/clk-pll.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 1595f02f610f..218c769c6d50 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -88,7 +88,6 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, frac = PARM_GET(p->width, p->shift, reg); rate += mul_u64_u32_shr(parent_rate, frac, p->width); - rate *= 2; } return div_u64(rate, n) >> od >> od2 >> od3; |