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authorJerome Brunet <jbrunet@baylibre.com>2018-05-15 19:36:52 +0300
committerJerome Brunet <jbrunet@baylibre.com>2018-05-21 12:31:59 +0300
commitde1ca2d07bdc3fb4a21991ca78b026324636f541 (patch)
treec095fbe88457380c235dda47f3d416317f12335b /drivers/clk/meson
parentbae1106c37c60661a94739b3f0a52138e227d604 (diff)
downloadlinux-de1ca2d07bdc3fb4a21991ca78b026324636f541.tar.xz
clk: meson: axg: let mpll clocks round closest
Let the mpll dividers achieve the closest rate possible, even if it means rounding the requested rate up. This is done to improve the accuracy of the rates provided by these plls to the audio subsystem Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson')
-rw-r--r--drivers/clk/meson/axg.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 5f5d468c1efe..bd4dbc696b88 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -461,6 +461,7 @@ static struct clk_regmap axg_mpll0_div = {
.width = 1,
},
.lock = &meson_clk_lock,
+ .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
@@ -507,6 +508,7 @@ static struct clk_regmap axg_mpll1_div = {
.width = 1,
},
.lock = &meson_clk_lock,
+ .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
@@ -553,6 +555,7 @@ static struct clk_regmap axg_mpll2_div = {
.width = 1,
},
.lock = &meson_clk_lock,
+ .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",
@@ -599,6 +602,7 @@ static struct clk_regmap axg_mpll3_div = {
.width = 1,
},
.lock = &meson_clk_lock,
+ .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "mpll3_div",