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| author | Alexandre Mergnat <amergnat@baylibre.com> | 2024-04-18 17:17:00 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-06-12 12:12:07 +0300 |
| commit | dd4b239184ee2bc2bf5a3327c7814e5d7a4de83b (patch) | |
| tree | 78db2d932f56406b23e805660e80c3701daf7bad /drivers/clk/qcom/clk-alpha-pll.c | |
| parent | 6f541a89ced8305da459e3ab0006e7528cf7da7b (diff) | |
| download | linux-dd4b239184ee2bc2bf5a3327c7814e5d7a4de83b.tar.xz | |
clk: mediatek: mt8365-mm: fix DPI0 parent
[ Upstream commit 4c0c087772d7e29bc2489ddb068d5167140bfc38 ]
To have a working display through DPI, a workaround has been
implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to
the DPI node. Shortly, that add an extra clock.
It seems consistent to have the "dpi0_sel" as parent.
Additionnaly, "vpll_dpix" isn't used/managed.
Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel".
The new clock tree is:
clk26m
lvdspll
lvdspll_X (2, 4, 8, 16)
dpi0_sel
mm_dpi0_dpi0
Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC")
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20231023-display-support-v3-12-53388f3ed34b@baylibre.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/clk-alpha-pll.c')
0 files changed, 0 insertions, 0 deletions