diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-01-13 15:05:40 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-01-19 07:50:01 +0300 |
| commit | 6fb03dd0b40aa83a3a04390ef539f1547b77ca1d (patch) | |
| tree | c89394e1ce6a7b7c8869a12d939c6a8e4979d6b8 /drivers/clk/qcom/clk-cpu-8996.c | |
| parent | fa0bc05f2f87eb84dba1977794048ee7b9ec6545 (diff) | |
| download | linux-6fb03dd0b40aa83a3a04390ef539f1547b77ca1d.tar.xz | |
clk: qcom: cpu-8996: fix PLL configuration sequence
Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux)
before PLL configuration. Switch them to the ACD afterwards.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-11-dmitry.baryshkov@linaro.org
Diffstat (limited to 'drivers/clk/qcom/clk-cpu-8996.c')
| -rw-r--r-- | drivers/clk/qcom/clk-cpu-8996.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 45015bb0dafe..244b72799214 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -432,13 +432,27 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, { int i, ret; + /* Select GPLL0 for 300MHz for both clusters */ + regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0xc); + regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0xc); + + /* Ensure write goes through before PLLs are reconfigured */ + udelay(5); + clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); + /* Wait for PLL(s) to lock */ + udelay(50); + qcom_cpu_clk_msm8996_acd_init(regmap); + /* Switch clusters to use the ACD leg */ + regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x2); + regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x2); + for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) { ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]); if (ret) |