diff options
author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2024-01-03 23:20:18 +0300 |
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committer | Sasha Levin <sashal@kernel.org> | 2024-03-27 01:17:08 +0300 |
commit | 5309b67c2ce9d5c99ad2f9ea3dd997874224e599 (patch) | |
tree | 09bf2d48b789b9b17bd83df20aee220794734681 /drivers/clk/qcom/dispcc-sdm845.c | |
parent | 103da4f1a1ec5ea05a691c4800bf84392f2dbfd3 (diff) | |
download | linux-5309b67c2ce9d5c99ad2f9ea3dd997874224e599.tar.xz |
clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times
[ Upstream commit 117e7dc697c2739d754db8fe0c1e2d4f1f5d5f82 ]
SDM845 downstream uses non-default values for GDSC internal waits.
Program them accordingly to avoid surprises.
Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # OnePlus 6
Link: https://lore.kernel.org/r/20240103-topic-845gdsc-v1-1-368efbe1a61d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/dispcc-sdm845.c')
-rw-r--r-- | drivers/clk/qcom/dispcc-sdm845.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index 735adfefc379..e792e0b130d3 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { static struct gdsc mdss_gdsc = { .gdscr = 0x3000, + .en_few_wait_val = 0x6, + .en_rest_wait_val = 0x5, .pd = { .name = "mdss_gdsc", }, |