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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2024-04-24 04:39:31 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-04-27 21:14:56 +0300 |
| commit | e90b5139da8465a15c3820b4b67ca9468dce93b4 (patch) | |
| tree | 30cbd53ff9187f23dcf5ea5a68bc866157705a4d /drivers/clk/qcom/dispcc-sm8650.c | |
| parent | 1113501cfb46d5c0eb960f0a8a9f6c0f91dc6fb6 (diff) | |
| download | linux-e90b5139da8465a15c3820b4b67ca9468dce93b4.tar.xz | |
clk: qcom: dispcc-sm8550: fix DisplayPort clocks
On SM8550 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-3-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/dispcc-sm8650.c')
0 files changed, 0 insertions, 0 deletions