summaryrefslogtreecommitdiff
path: root/drivers/clk/qcom/gcc-msm8996.c
diff options
context:
space:
mode:
authorAbhishek Sahu <absahu@codeaurora.org>2017-09-28 20:50:40 +0300
committerStephen Boyd <sboyd@codeaurora.org>2017-12-14 00:45:30 +0300
commit28d3f06e56baa9c6e2c8e1d9e5fd663138c08b92 (patch)
treef241a2002d9e181b25cf83b48ded3472e7712a4c /drivers/clk/qcom/gcc-msm8996.c
parent4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff)
downloadlinux-28d3f06e56baa9c6e2c8e1d9e5fd663138c08b92.tar.xz
clk: qcom: support for alpha pll properties
Alpha PLL is a generic name used for QCOM PLLs which uses L and Alpha values for configuring the integer and fractional part. QCOM SoCs use different types of Alpha PLLs for which basic software configuration part is common with following differences. 1. All these PLLs have the same basic registers like PLL_MODE, L_VAL, ALPHA_VAL but some of the register offsets are different between PLLs types. 2. The dynamic programming sequence is different in some of the Alpha PLLs 3. Some of the PLLs don’t have 64 bit config control, 64 bit user control, VCO configuration, etc. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/gcc-msm8996.c')
-rw-r--r--drivers/clk/qcom/gcc-msm8996.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 7ddec886fcd3..5d7451209206 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -227,6 +227,7 @@ static struct clk_fixed_factor xo = {
static struct clk_alpha_pll gpll0_early = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
@@ -252,6 +253,7 @@ static struct clk_fixed_factor gpll0_early_div = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]){ "gpll0_early" },
@@ -262,6 +264,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
static struct clk_alpha_pll gpll4_early = {
.offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
@@ -276,6 +279,7 @@ static struct clk_alpha_pll gpll4_early = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_names = (const char *[]){ "gpll4_early" },