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| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-07-03 21:20:10 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-08-14 05:51:04 +0300 |
| commit | a6f1e8623836bb6ce64c347d110ecb6259ae73c4 (patch) | |
| tree | 6a0e03d8f22741c500d982b4a5c01bceb0891fc6 /drivers/clk/qcom/gcc-msm8998.c | |
| parent | 03f1b83d89851abdd5c490f873124a1ba2a6ae33 (diff) | |
| download | linux-a6f1e8623836bb6ce64c347d110ecb6259ae73c4.tar.xz | |
clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks
Some branch clocks are governed externally and we're only supposed to
send a request concerning their shutdown, not actually ensure it happens.
Use the BRANCH_HALT_SKIP define to skip checking the halt bit.
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-6-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/gcc-msm8998.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8998.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index cccb19cae481..ef410f52f09f 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2112,7 +2112,7 @@ static struct clk_branch gcc_gp3_clk = { static struct clk_branch gcc_bimc_gfx_clk = { .halt_reg = 0x46040, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x46040, .enable_mask = BIT(0), @@ -2125,7 +2125,7 @@ static struct clk_branch gcc_bimc_gfx_clk = { static struct clk_branch gcc_gpu_bimc_gfx_clk = { .halt_reg = 0x71010, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x71010, .enable_mask = BIT(0), @@ -2151,7 +2151,7 @@ static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { static struct clk_branch gcc_gpu_cfg_ahb_clk = { .halt_reg = 0x71004, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x71004, .enable_mask = BIT(0), |