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authorStephen Boyd <sboyd@kernel.org>2023-10-27 22:21:17 +0300
committerStephen Boyd <sboyd@kernel.org>2023-10-27 22:21:17 +0300
commit0dea4e30fedad73ce3223b4d3d546fafc1aa77a6 (patch)
tree5a77c64169ea3e9b05d4e3210d18e0f3ca48e578 /drivers/clk/qcom/mmcc-msm8974.c
parent0bb80ecc33a8fb5a682236443c1e740d5c917d1d (diff)
parente0e6373d653b7707bf042ecf1538884597c5d0da (diff)
downloadlinux-0dea4e30fedad73ce3223b4d3d546fafc1aa77a6.tar.xz
Merge tag 'qcom-clk-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson: - Initial support for the SM4450 Global Clock Controller and RPMh clock controllers - Drop CLK_SET_RATE_PARENT for clocks with fixed-rate GPLLs across a variety of IPQ platforms - Add missing parent of APCS PLL on IPQ6018 - Add I2C QUP6 clk on IPQ6018 but mark it critical to avoid problems with RPM - Implement safe source switching for a53pll and use on IPQ5332 - Add support for Stromer Plus PLLs - Switch SM8550 Video and GPU clock controllers to use OLE PLL configure method - Non critical fixes to halt bit checks - Add SMMU GDSC for MSM8998 - Fix possible integer overflow in RCG frequency calculation code - Remove RPM managed clks from MSM8996 GCC driver - Add Camera Clock Controller on SM8550 - Add HFPLL configuration for the three HFPLLs in MSM8976 - Switch MSM8996 CBF clock driver's remove function to return void * tag 'qcom-clk-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (36 commits) clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks clk: qcom: gcc-ipq6018: add QUP6 I2C clock clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll clk: qcom: clk-alpha-pll: introduce stromer plus ops clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure clk: qcom: Replace of_device.h with explicit includes clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect clk: qcom: cbf-msm8996: Convert to platform remove callback returning void clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src clk: qcom: Add GCC driver support for SM4450 dt-bindings: clock: qcom: Add GCC clocks for SM4450 ...
Diffstat (limited to 'drivers/clk/qcom/mmcc-msm8974.c')
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 1f3bd302fe6e..a31f6cf0c4e0 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2170,22 +2170,6 @@ static struct clk_branch mmss_s0_axi_clk = {
},
};
-static struct clk_branch ocmemcx_ahb_clk = {
- .halt_reg = 0x405c,
- .clkr = {
- .enable_reg = 0x405c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "ocmemcx_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &mmss_ahb_clk_src.clkr.hw
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch ocmemcx_ocmemnoc_clk = {
.halt_reg = 0x4058,
.clkr = {
@@ -2503,7 +2487,6 @@ static struct clk_regmap *mmcc_msm8226_clocks[] = {
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
- [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
@@ -2660,7 +2643,6 @@ static struct clk_regmap *mmcc_msm8974_clocks[] = {
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
- [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
[OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,