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authorStephen Boyd <sboyd@kernel.org>2023-08-31 00:39:58 +0300
committerStephen Boyd <sboyd@kernel.org>2023-08-31 00:39:58 +0300
commit41680df0975e04b959a28bf6ab85fd6a307ae0ea (patch)
tree36baf601d2281987d5dcaa8d04ccf3e11f548247 /drivers/clk/qcom/mmcc-msm8974.c
parent3462100cf38b192e7ef1b3a11c4f6d64c5e8066d (diff)
parent75d1d3a433f0a0748a89eb074830e9b635a19fd2 (diff)
downloadlinux-41680df0975e04b959a28bf6ab85fd6a307ae0ea.tar.xz
Merge branch 'clk-qcom' into clk-next
* clk-qcom: (87 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks ...
Diffstat (limited to 'drivers/clk/qcom/mmcc-msm8974.c')
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index a7acdef5a14e..1f3bd302fe6e 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2425,6 +2425,16 @@ static struct gdsc oxilicx_gdsc = {
.pwrsts = PWRSTS_OFF_ON,
};
+static struct gdsc oxili_cx_gdsc_msm8226 = {
+ .gdscr = 0x4034,
+ .cxcs = (unsigned int []){ 0x4028 },
+ .cxc_count = 1,
+ .pd = {
+ .name = "oxili_cx",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *mmcc_msm8226_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -2514,6 +2524,7 @@ static struct gdsc *mmcc_msm8226_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
[CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
+ [OXILICX_GDSC] = &oxili_cx_gdsc_msm8226,
};
static const struct regmap_config mmcc_msm8226_regmap_config = {