diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-12-08 12:56:58 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-01-24 12:11:50 +0300 |
| commit | 584d29912db27e56eaaccd225e283e1f429e4f83 (patch) | |
| tree | afab810123a716404755045c64e2f372c98c9dd5 /drivers/clk/renesas/r8a779g0-cpg-mssr.c | |
| parent | 1c052043c79af5f70e80e2acd4dd70904ae08666 (diff) | |
| download | linux-584d29912db27e56eaaccd225e283e1f429e4f83.tar.xz | |
clk: renesas: r8a779g0: Add custom clock for PLL2
Currently the PLLs are modeled as fixed factor clocks, based on initial
settings. However, enabling CPU boost clock rates requires increasing
the PLL clock rates.
Add a custom clock driver to model the PLL clocks on R-Car Gen4, and use
it for PLL2 on R-Car V4H. This allows the Z clock (Cortex-A76 core
clock) to request PLL rate changes, and enable boost mode for the High
Performance mode. For now this is limited to integer multiplication
modes.
Note that the definition for CPG_PLLxCR0_NI uses the value for R-Car V4H.
On R-Car S4-8, the integer and fractional multiplication fields are one
bit larger resp. smaller, but R-Car S4-8 does not support High
Performance mode.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/76a5952900a6e15604c640bc8a27762e0e936677.1670492384.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas/r8a779g0-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a779g0-cpg-mssr.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 745ff9214fe8..48d9f34bbf37 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -66,13 +66,13 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ - DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), - DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), - DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), - DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), - DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), - DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), - DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2_VAR, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), |