diff options
| author | Phil Edworthy <phil.edworthy@renesas.com> | 2022-05-03 14:55:54 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 13:12:33 +0300 |
| commit | 8090bea32484d45b19b57577dee4519cbc28571c (patch) | |
| tree | 066f40efc0960719b1f3869e0384c4eb1963b058 /drivers/clk/renesas/rzg2l-cpg.c | |
| parent | 63804400f2a5ababe596b4ec908321d6b54f45aa (diff) | |
| download | linux-8090bea32484d45b19b57577dee4519cbc28571c.tar.xz | |
clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
single bit per module.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-10-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 48265276d169..f8a68bbc76f2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1177,8 +1177,16 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, const struct rzg2l_cpg_info *info = priv->info; unsigned int reg = info->resets[id].off; u32 bitmask = BIT(info->resets[id].bit); + s8 monbit = info->resets[id].monbit; - return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + if (info->has_clk_mon_regs) { + return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + } else if (monbit >= 0) { + u32 monbitmask = BIT(monbit); + + return !!(readl(priv->base + CPG_RST_MON) & monbitmask); + } + return -ENOTSUPP; } static const struct reset_control_ops rzg2l_cpg_reset_ops = { |