diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-02-05 11:40:06 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-10 16:34:58 +0300 |
| commit | a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd (patch) | |
| tree | a90d6bd381ba4a19c2e448c31010cc70b02b94d8 /drivers/clk/renesas/rzg2l-cpg.c | |
| parent | fbf4ae93c2bca96035b2c36f408b0616403ede10 (diff) | |
| download | linux-a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd.tar.xz | |
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers to
control clocks and resets for the DRP-AI block.
Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same
between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take
care of the DRP-AI clocks/resets.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index edd0abe34a37..486d0656c58a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -953,6 +953,12 @@ static const struct of_device_id rzg2l_cpg_match[] = { .data = &r9a07g044_cpg_info, }, #endif +#ifdef CONFIG_CLK_R9A07G054 + { + .compatible = "renesas,r9a07g054-cpg", + .data = &r9a07g054_cpg_info, + }, +#endif { /* sentinel */ } }; |