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authorFinley Xiao <finley.xiao@rock-chips.com>2018-11-14 18:45:49 +0300
committerHeiko Stuebner <heiko@sntech.de>2018-11-15 14:11:37 +0300
commita9f0c0e563717b9f63b3bb1c4a7c2df436a206d9 (patch)
tree28bcfcd73e96c19d655ceeb7279c4cfd9a19cb14 /drivers/clk/rockchip
parent8b19faf6fae2867e2c177212c541e8ae36aa4d32 (diff)
downloadlinux-a9f0c0e563717b9f63b3bb1c4a7c2df436a206d9.tar.xz
clk: rockchip: fix rk3188 sclk_smc gate data
Fix sclk_smc gate data. Change variable order, flags come before the register address. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Johan Jonker <jbx9999@hotmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 08b42b053fce..dee13dd20ba4 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -391,8 +391,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
* Clock-Architecture Diagram 4
*/
- GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
- RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
+ GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
+ RK2928_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,