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authorElaine Zhang <zhangqing@rock-chips.com>2017-08-08 10:19:33 +0300
committerHeiko Stuebner <heiko@sntech.de>2017-08-08 18:28:57 +0300
commitb75f38451a5d7b6893087ca6c0ec7b01491f60b0 (patch)
tree08de4ad2d6287c03c2f1b80cbdd3ff9db2217b42 /drivers/clk/rockchip
parenta52394e9a0a8cea8e1501b3860e067d54e43c8de (diff)
downloadlinux-b75f38451a5d7b6893087ca6c0ec7b01491f60b0.tar.xz
clk: rockchip: add some critical clocks for rv1108 SoC
the bus/periph/nclk_ddrupctl/pclk_ddrmon/pclk_acodecphy/pclk_pmu no driver to handle them, Chip design requirements for these clock to always on. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk-rv1108.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index f907b67745e4..d1065dd9f442 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -776,10 +776,16 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
static const char *const rv1108_critical_clocks[] __initconst = {
"aclk_core",
- "aclk_bus_src_gpll",
+ "aclk_bus",
+ "hclk_bus",
+ "pclk_bus",
"aclk_periph",
"hclk_periph",
"pclk_periph",
+ "nclk_ddrupctl",
+ "pclk_ddrmon",
+ "pclk_acodecphy",
+ "pclk_pmu",
};
static void __init rv1108_clk_init(struct device_node *np)