summaryrefslogtreecommitdiff
path: root/drivers/clk/samsung
diff options
context:
space:
mode:
authorMarek Szyprowski <m.szyprowski@samsung.com>2017-01-26 15:37:53 +0300
committerSylwester Nawrocki <s.nawrocki@samsung.com>2017-01-27 13:34:00 +0300
commit698e0d1d22346ef03d7a13fcd9c2cc86a24bf317 (patch)
tree4effec2a5d8cc0b65e1c9098537a7621491bfbf4 /drivers/clk/samsung
parent5ccb58968bf7f46dbd128df88f71838a5a9750b8 (diff)
downloadlinux-698e0d1d22346ef03d7a13fcd9c2cc86a24bf317.tar.xz
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
Default clock configuration applied by the bootloader for TM2 and TM2e boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such configuration for those boards with 'assigned-clock-*' properties, parameters for those two additional rates are needed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index e11736f1625f..3feaea8be40e 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst =
PLL_35XX_RATE(350000000U, 350, 6, 2),
PLL_35XX_RATE(333000000U, 222, 4, 2),
PLL_35XX_RATE(300000000U, 500, 5, 3),
+ PLL_35XX_RATE(278000000U, 556, 6, 3),
PLL_35XX_RATE(266000000U, 532, 6, 3),
+ PLL_35XX_RATE(250000000U, 500, 6, 3),
PLL_35XX_RATE(200000000U, 400, 6, 3),
PLL_35XX_RATE(166000000U, 332, 6, 3),
PLL_35XX_RATE(160000000U, 320, 6, 3),